Konferensartikel

In this paper we show how an ef?cient implementation of genetic algorithms can be done on Field Programmable Gate Array i.e. on programmable hardware using the latest hardware design language aiding veri?cation. A four-way number partitioning problem of 128 unsigned 16-bit integers is used as a test case of the implementation. However, other similar problems could be solved using the proposed approach. The design was implemented using a combination of reusable veri?ed intellectual property cores for arithmetic operations and VHDL to describe the genetic algorithm operators in register transfer level. The register transfer level components were veri?ed in ModelSim using SystemVerilog assertions and cover groups. Test results show signi?cant improvements in performance compared to C language implementation running on a core i-7 desktop computer.

genetic algorithms, veri?cation, FPGA, System on Chip (SoC)