Magnus Karlsson
University of Kalmar, Sweden
Mark Vesterbacka
Linköping University, Sweden
Wlodek Kulesza
University of Kalmar, Sweden
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Ingår i: GigaHertz 2003. Proceedings from the Seventh Symposium
Linköping Electronic Conference Proceedings 8:28, s.
Publicerad: 2003-11-06
ISBN:
ISSN: 1650-3686 (tryckt), 1650-3740 (online)
In this paper; a new robust non-overlapping twophase clock generator with adjustable duty cycle is proposed. The generator is based on a differential negative edge trigged D flip-flop and has small area and power consumption. The maximal clock rate and delay are also improved reaching a clock frequency of 1.0 GHz in a standard 0.35 µm CMOS process. The new clock generator is inherently glitch and spike free and robust against slow clock transitions; that reduces the design effort significantly.
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[3] M. Karlsson; and M. Vesterbacka; “A RobustNon-Overlapping Two-Phase Clock Generator;” in Proc. of Swedish System on Chip Conference SSoCC’03; Sundbyholms slott; Eskilstuna; Sweden; Mars 8-9; 2003.
[4] M. Karlsson; M. Vesterbacka; “Implementation of Bit-Serial Adders using Robust Differential Logic;” in Proc. IEEE Conf. NORCHIP’97. pp. 366-373; Tallin; Estonia; Nov.; 1997.
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